1. Field of the Invention
The present invention relates to the arrangement of DMA, interrupt and timer functions between a central peripheral mounted on the system board of a multiprocessor computer system and a distributed peripheral mounted on each microprocessor board to implement symmetrical processing.
2. Description of the Related Art
The personal computer industry is evolving quickly due to the increasing demand for faster and more powerful computers. Historically, computer systems have developed as single microprocessor, sequential machines which process one instruction at a time. However, performance limits are being reached in single microprocessor computer systems so that a major area of research in computer system architecture is multiprocessing. Multiprocessing involves a computer system which includes multiple microprocessors that work in parallel on different problems or different parts of the same problem. The incorporation of several microprocessors in a computer system introduced many design problems that were not present in single microprocessor architectures.
For example, the SystemPro by Compaq Computer Corp., which was based on the i386 or i486 microprocessors by Intel Corp., typically included a plurality of buses such as a host bus for interfacing one or more processors with main memory, an expansion bus such as the Industry Standard Architecture (ISA) or Extended ISA (EISA) bus which was used to interface with one or more optional and external plug-in logic circuit boards, and an X bus for interfacing with a plurality of peripheral devices such as a keyboard and a floppy disk controller. The processors typically shared the host bus for easy access to the main memory. Although it was desirable that each processor be relatively independent so that each processor could perform any particular task, design limitations have heretofore resulted in asymmetric systems.
In particular, the SystemPro included an EISA system peripheral (ESP) based on the 82357 integrated system peripheral (ISP) by Intel. The ESP incorporated many functions central to the entire system so that it was conveniently located on the expansion bus. The ESP included a programmable interrupt controller (PIC), an EISA bus interface, five internal timers for system timing functions, a DMA controller, a RAM refresh generator, NMI logic for indicating error conditions and other service conditions requiring immediate attention, and a system arbiter, which evaluates requests for the EISA bus from a plurality of sources such as DMA channels, refresh requests, and CPU requests as well as other bus master requests.
Since the ESP was centrally located and connected to the EISA bus, it was only feasible that one processor handle all of the maskable and nonmaskable interrupts and the timer functions as well as programming the DMA controller. Thus, only one processor interfaced with the ESP and had access to its functions while the remaining processor did not have access to the ESP and was limited to the remaining functions of the computer system. One reason for this asymmetric design was the difficulty in determining which particular interrupt was received by the ESP and thus the inability to determine which particular processor was supposed to handle the function. For example, the ESP received a plurality of interrupts but only provided one interrupt signal, so that there was no way of determining which particular interrupt was received and thus no way of assigning the proper processor to handle the interrupt. Another difficulty arose if a second processor interrupted the DMA programming sequence of a first processor. The second processor would alter the byte pointer and terminal count bits which would cause errors in programming when the first processor continued its programming sequence. Thus, although it was convenient to assign one processor to handle all of the ESP functions resulting in an asymmetric design, this design also restricted flexibility of programming, which degraded overall system performance.
Therefore, it is desirable to allow each of the other processors in a multiprocessor system access to certain of the functions previously located in the ESP to allow system flexibility so that a programmer can assign any task to a particular processor. Furthermore, it would be desirable to divide the functions between the processors in a compatible manner.